DefinePK

DefinePK hosts the largest index of Pakistani journals, research articles, news headlines, and videos. It also offers chapter-level book search.

Select Collection

4x4 Bit Multiplier Designs using Different CMOS Schematics, and their Comparison

Article Information

Get PDF View Article
Login to Add in Library

Title: 4x4 Bit Multiplier Designs using Different CMOS Schematics, and their Comparison

Authors: Kaynat Rana, Asim Niaz, Sumbol Hanif, Muhammad Touqeer Ali

Journal: Technical Journal

HEC Recognition History
Category From To
Y 2024-10-01 2025-12-31
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
Y 2020-07-01 2021-06-30
X 2019-12-20 2020-06-30
Y 2013-08-11 2019-12-19
Z 2009-02-10 2013-08-10

Publisher: University of Engineering & Technology, Taxila

Country: Pakistan

Year: 2019

Volume: 24

Issue: 4

Language: English

Categories
Electrical Engineering (5972) Computer Engineering (1270) VLSI Design (122) Digital Logic (5) Microelectronics (45)

Abstract

In this paper, low power and high speed 4x4 bit multipliers are presented. The full adder and a half adder blocks used in these multipliers are designed using adiabatic and transmission gate techniques respectively. The multiplier circuit is implemented using Dadda algorithm. This circuit is simulated in 1P-9M Low-K UMC 90nm CMMOS process technology (cadence Virtuoso). The circuit operates at a clock frequency of 5.46 and 8.54 GHz and dynamic average power of 2.667 and 1.139 mW respectively, at room temperature of 27˚C and 1.9V supply voltage.

Paper summary is not available for this article yet.

Loading PDF...

Loading Statistics...