DefinePK

Abstract

Forcommunication systems, error detectors are required to make sure that error free signal is passed whiletransmitting/receiving. This error detection is resolvedby a basic parity generator and parity checker in QCA.Butthese parity checkers cannot detect all forms of error. It checks whether it is an odd or even parity. To overcome thelimits of parity checker, cyclic redundancy check (CRC) will be analysed and can be designed using QCA.Currently, QCA standsa assuring replacement for CMOStechnology. In QCA,the operation isdirected bytheelectron’s position. The consumption of power in QCA is less and the operation of clock frequency is high overtraditionalCMOS. Also with technology reaching Nano-scale, CMOS does not function perfect. CRC’s areespecially useful in digital circuits such as phase detectors, code converters and error detection & correctioncircuits. In this paper, QCA Designer tool ver. 2.0.3 has been used for the simulation of the design.