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Layout design and simulation for analog neural network circuit using COMOS technology 0, 35 µm

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Title: Layout design and simulation for analog neural network circuit using COMOS technology 0, 35 µm

Authors: Robby Kurniawan Harahap, Brahmantyo Heruseto, Eri Prasetyo, Hamzah Afandi

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2014

Volume: 9

Issue: 10

Language: English

Categories
Electrical Engineering (5972) Neural Networks (134) VLSI Design (122) Analog Circuits (11) Circuit Design (53)

Abstract

In this paper, a layout design for analog neural network designed using mentor graphics software based technology will ICFlow 0, 35. By using mentor graphics software ICFlow designing a layout of analog neural network component to a high speed camera and also perform simulations layout. Multiplier designing layouts, Op-amp layout, and Sigmoid layout. To generate the layout design rule check process performed (DRC) and Layout Versus Schematic (LVS). Resulting layout correctly according to the rules of technology.

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