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Design of modified explicit pulse data-close-to-output flip-flop


Article Information

Title: Design of modified explicit pulse data-close-to-output flip-flop

Authors: A. Sathishkumar, S. Saravanan, R. Sakthivel

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2015

Volume: 10

Issue: 22

Language: English

Categories

Abstract

Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules such as register file, shift register, and first in- first out. In this paper we proposed a low power consumed and less area pulse triggered flip-flop. This design uses 23 transistors this reduces the area complexity by 3 transistors comparing with existing ep-DCO. The new flip-flop can save up to 74% of the energy with the same speed as that for the existing ep-DCO and can save up to 69% of the energy with the same speed as that for the CDFF.


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