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Memory requirements for hardware implementation of the H.264 decoder modules


Article Information

Title: Memory requirements for hardware implementation of the H.264 decoder modules

Authors: Karthikeyan C., Rangachar

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2015

Volume: 10

Issue: 22

Language: English

Categories

Abstract

To address the increasing demand for higher resolution and frame rates, processing speed (i.e. performance) and area cost need to be considered in the development of next generation video coding. Context-based adaptive binary arithmetic coding (CABAC) is the major entropy-coding algorithm employed in H.264/AVC. In this paper, subinterval reordering is proposed for the arithmetic decoder to increase the processing speed and to lower the frequency of memory access. Modification of the motion vector difference (MVD) context selection is proposed to reduce memory requirements and speed up the memory access. These above two methods and architecture optimizations are non-standard compliant and this proposed work is incorporated using buffers and registers for temporary storage and processing of the data. The speed of operation is improved by more than 50% with respect to normal operation.


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