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Modified booth multiplier architecture using new (1, 1, 1) adder

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Title: Modified booth multiplier architecture using new (1, 1, 1) adder

Authors: Anu Mehra, Priyank Kularia, Aditya Sharma, Garima Batra, Achintya Rawat, Nidhi Gaur

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2015

Volume: 10

Issue: 17

Language: English

Categories
Electrical Engineering (5972) Wireless Communication (410) Analysis (236) Computer Engineering (1270) Environmental Science (16313) Computer Architecture (114) VLSI Design (122) Monitoring (18) Digital Circuits (26) Electromagnetic Fields (19)

Abstract

In this paper an alternate implementation of the modified Booth algorithm is presented where groups of the partial product terms are summed using parallel prefix adders proposed by Harris et al. Comparative analysis of these adders in terms of power, delay and LUTs is performed. A modified 16 bit multiplication process using Radix 4 Booth Algorithm is proposed and results with respect to Kogge Stone and New (1, 1, 1) adder are computed. Simulation results are carried out on Xilinx Vivado Version14.2 on Artix 7 Board.

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