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Title: Embedded shift invert transition coding for parallel links
Authors: B. SivachandraMahalingam, R. Ganesh, B. Parthasarathy, M. Dhinesh
Journal: ARPN Journal of Engineering and Applied Sciences
Publisher: Khyber Medical College, Peshawar
Country: Pakistan
Year: 2015
Volume: 10
Issue: 11
Language: English
Power dissipation in a chip mostly depends only on switching activity in a chip (high to low vice versa).Various gating and Encoding schemes are introduced to reduce the unnecessary switching activity of a chip during serial data transmission in a network. But the Encoding methods results in increased bit size and reduces only 15% of the power dissipation (loss). This paper proposed to reduce the switching transitions in a wider Bus, Embedded Shift Invert Coding technique is designed and simulated and its performance is compared with the existing Bus Encoding Techniques.The proposed Embedded Shift Invert Coding technique is first designed and simulated by partitioning the Bus data into two equal width data partitions and applying conventional Shift Invert Coding technique to each of the data partitions. The analysis and simulation results indicate that the Proposed Coding scheme produces a low bit transition for different kinds of data patterns (INV, Left Shift, Right Shift and Normal).
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