DefinePK

Abstract

A phase-locked loop (PLL) is widely employed in wire line and wireless communication systems. The poor device matching and leakage current vary the common-mode voltage of a ring-based voltage-controlled oscillator (DCO) wide frequency range. It may limit the oscillation frequency range of a DCO and causes a DCO not to oscillate in a worst case. To realize a wide-range PLL, the divider following a DCO should operate between the highest and lowest frequencies. When a PLL works at a higher frequency which the static circuits cannot operate, dynamic circuits are needed. A true-single-phase-clocking (TSPC) divider is widely used to realize a prescaler for this PLL. A TSPC prescaler must work over a wide frequency range to cover the process and temperature variations. For a TSPC prescaler, the undesired leakage currents may limit its frequency range or alter the original states of the floating nodes to have a malfunction. The leakage current and current mismatch in a charge pump (CP) will degrade the reference spur and jitter significantly. In the previous method to overcome the above problems, a self-healing divide-by-4/5 prescaler and a self-healing DCO used. A time-to digital converter (TDC) and a 4-bit encoder are used to quantize the phase error and digitally calibrate the CP. In the existing method the key parameter is to be changed is the modulus value of the prescaler. By changing the value of the prescaler the PLL frequency range will be extended.