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Abstract

In this paper the Darlington pair and internal circuit biasing technique is used for the enhancing the slew rate as well as gain and unity gain bandwidth. The proposed CMOS Op-Amp has been verified through Cadence Analog Design Environment with spectre simulator in the standard 45nm CMOS process. In this proposed circuit the gain stage is divided in two parts, first is modified gain stage and second one is Darlington pair stage. The effects of both the modified gain stage and Darlington stage currents are considered in this circuit and a simple analytical expression is given in terms of the load and compensation capacitors. The new scheme allows the slew rate to be increased with only a small increase in static power consumption. At the dc power dissipation of 0.76 mW, the proposed circuit achieves a slew rate of 2791V/μs, gain of 70 dB and unity gain bandwidth of 1.74 GHz.