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Input vector monitoring concurrent BIST architecture using modified SRAM cells

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Title: Input vector monitoring concurrent BIST architecture using modified SRAM cells

Authors: B. Divyapreethi, T. Karthik

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2015

Volume: 10

Issue: 9

Language: English

Keywords: dynamic power dissipationInput vector monitoringconcurrent BISTmodified SRAM

Categories
Computer Science (14978) Built-In Self-Test (4) SRAM (6) Power Dissipation (1) VLSI Design (122)

Abstract

Input vector monitoring concurrent BIST performs two modes of operation, normal mode and test mode During test mode the test generator value is compared with higher order bits and the output is given to comparator circuit. During normal mode the inputs to the CUT are driven from the normal inputs. The modified SRAM is used to reduce the switching activity hence the dynamic power dissipation can be reduced. The output is verified by response verifier (RV) and the fault is identified using testing. The operating speed is faster since the operation is carried out as parallel process and it is suitable for all the type of IC’s.

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