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Abstract

This paper presents a glitch free NAND based digitally controlled delay lines for the avoidance of glitches by using different driving circuits. In glitch free NAND based DCDL, driving circuits are used to generate the control bits which consumes considerable amount of power and delay time. Driving techniques suggested here are dual edge triggered sense amplifier based flip-flop and NIKOLIC sense amplifier based flip-flop, which comparatively have reduced power consumption and delay time. The proposed NAND based DCDL have been designed in 90nm CMOS technology and various performances of these techniques are compared by the simulation parameters like power, area and delay. In addition, the proposed DCDL is adopted in phase locked loop.