DefinePK

Abstract

Edge detection is one of the most commonly used operations in image analysis particularly in the areas of feature extraction. Edge in an image indicates the boundaries between overlapping objects. An edge represents the boundary between an object and the image background, hence if the edges are identified with high accuracy in an image then all its objects can be located and basic properties of an image can also be measured. An edge can also be defined as a set of connected pixels that forms a boundary between two disjoints regions. Edge detection is a basic method of segmenting an image into regions of discontinuity. The data which are extracted in edge detection is too large, so to achieve the high speed of image processing is a difficult task. To solve this problem, a distributed canny edge detection algorithm is proposed that results in significant reduction of memory requirements with decreased latency and increased throughput with no loss in edge detection performance as compared to the original canny algorithm. In addition, the new algorithm uses a non uniform gradient magnitude histogram to compute block-based hysteresis thresholds. The resultant block-based algorithm has significant reduction in latency and can be easily integrated with other block-based image codecs then it is made capable of supporting fast edge detection of images and videos with high resolution rate, including full-HD videos as the latency is changed as a function of the block size instead of the frame size. In addition to that, quantitative conformance evaluations and subjective tests show that the edge detection performance of the proposed algorithm is better than the original frame-based algorithm, especially for noisy images. Furthermore, FPGA-based hardware architecture of our proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Virtex-5 FPGA. Simulation results are dispensed to illustrate the performance of the proposed distributed Canny edge detector. The FPGA simulation results displays that we can process a 512×512 image in 0.287ms at a clock rate of 100 MHz.