DefinePK

Abstract

Power is an inevitable curb on digital design of emerging technologies. The down-scaling of transistor geometric paves the way for the curtailment of power consumption. Out of all the leakage components, subthreshold leakage current is the major shell out in static power dissipation. The subthreshold leakage power is analyzed in conventional circuit of 16-bit Carry Look Ahead Adder (CLA). The paper aims on a novel concept of Short Pulse Power Gated Approach (SPOGA), a leakage power reduction technique implemented particularly for low duty cycle (Example: Wireless Sensor Networks, Burst Mode type, etc.,) applications. The values of power consumption of the circuit are interpreted from the transient analysis of the circuit using 90nm technology in Cadence GPDK.