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Abstract

This paper presents a VLSI implementation of reduced hardware-complexity and reconfigurable signal detector for MIMO (Multiple-Input Multiple-Output) systems.MACROBUTTON NoMacro In recent wireless communication system, MIMO technique is being adopted to meet the rapidly increasing demands for the multimedia services and to achieve better QoS(Quality of Service). Maximum likelihood (ML) detection is the optimal hard decision detection for MIMO systems. FPGA implementation of ML detector becomes infeasible as its complexity grows exponentially with the number of antennas. Therefore, we propose a modified K-best detector algorithm which employs parallel and distributed sorting strategy that has a constant throughput and near-ML detection solution. The proposed MIMO detector was implemented targeting Xilinx Virtex 6 device for a 2x2, 4 QAM system and it achieves throughput of 12.23Mbps. The resource utilization results are listed and compared with the existing algorithm. The total on-chip power estimated is 1.57W.