DefinePK

Abstract

The system-on-chip (SoC) revolution imposes a threat in the area of power dissipation by challenging designing as well as the testing process. Basically, a circuit or a system consumes more power in test mode than in normal mode. This increase in test power is due to increase in the number of switching activity in the device due to test pattern used for testing. This extra power consumption gives rise to severe hazards in circuit reliability and also can provoke instant circuit damage. Many techniques are available for test data compression. The “Proposed Tanimoto distance Based Reordering” technique is a modification to the earlier proposed “Hamming Distance based Reordering - Columnwise Bit Filling and Difference vector”.