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Abstract

In this work, we investigate the impact of different ground plane (GP) structures of the ultra-thin body and buried oxide SOI MOSFETs (UTBB SOI MOSETs) on the digital and analog figures-of-merits (FoM) with gate length of Lg= 25 nm and 10 nm. Different GP structures are found to have significant impact on the drain-induced barrier lowering (DIBL) while the impact on subthreshold-slope (SS) is negligible. Incorporation of localized ground plane of p-type in the substrate underneath the channel (referred herein as GP-B structure) provides excellent results of DIBL as of the incorporation of n+/p+/n+ structure underneath the buried-oxide (referred herein as GP–C structure). The effective suppression of the substrate depletion effect is observed with showing no increase in the potential under the channel for both GP–B and GP-C structures between low (Vd=20 mV) and high (Vd=1 V) drain bias. However, as the simulations were extended to analog FoM, it is found that only GP-B structure managed to maintain excellent result in terms of voltage gain, Av while GP-C showed deteriorations due to an early increase in output conductance, gdat low frequency.