DefinePK

Abstract

On-chip communication concept is the basic requirement for modern systems that offers high throughput. Network-on-chip routers provide essential routing functionality for effective global on -chip communication with low complexity and relatively high performance. Arbiters are used in No C router when number of input ports is request for the same output port. Recently, the Round Robin Arbiter and Matrix Arbiter are the basic building block for high speed switches / routers, receives a new attention with the advent of the Network-on-chip. In this paper, we compare the performance of these two arbiters in VLSI and tested in FPGA platform. Through the experiment result, we found that the resource utilization of Matrix arbiter is less compared to Round Robin Arbiter. For example for the input request 32 of the arbiter, the number of slices used for MA is 488 slices, for RRA is 2388 slices, Look Up Tab le mappings for MA is 921, for RRA is 2652 and the number of flip flops used for MA is 401 and the number of flip flops used for RRA is 1438. However the RRA has less frequency than the Matrix Arbiter. The performance evolution is achieved by allowing routing function for each input port, distributed arbiters and output port which gives high level of parallelism. When designing a network-on-chip arbiter, the trade off between the two mechanisms should be considered.