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Design and performance analysis of Asynchronous counter using Feynman gate based T Flip Flop


Article Information

Title: Design and performance analysis of Asynchronous counter using Feynman gate based T Flip Flop

Authors: Gopalakrishnan M., C. Karthick

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2016

Volume: 11

Issue: 17

Language: English

Categories

Abstract

The design of circuits using reversible logic has resulted in optimization of power dissipation. The reversible computation has found its application in low power circuit design, DNA computing and Quantum computing. Basic reversible gates can be used to realize Boolean functions in reversible logic design. A T Flip flop has been designed in this work and used to implement an Asynchronous counter. The optimized T Flip Flop design has been compared with the existing T flip flop. The design proposes reduced power dissipation and gate delay and is significantly lower than the existing system. The design is developed on Xilinx ISE 9.1i, the simulation was done on ModelSim and Xilinx Xpower was used for power analysis.


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