DefinePK

Abstract

In the development of the microprocessor architecture, the focus is given more on the microprocessor s performance parameters such as speed, size, cost and power consumption, while less attention is paid to the reliability of data. With the advancement of semiconductor technology node, internal components of a microprocessor are also prone to soft error due to sensitivity to glitches and noise. This paper presents an internal implementation of the fault-tolerance design for a low-end microcontroller. The UTeMRISC Microcontroller is chosen for this research and the fault-tolerance is designed based on the error correction code (ECC). The design is focused on the implementation of Hamming Code and Single-Error-Correction Double-Error-Detection (SEC-DED) Code that are synthesizable in the Field Programmable Gate Array (FPGA). To evaluate the performance and functionality of the design, a number of pre-defined faults are injected into the Fault-Tolerant module at three different locations in the UTeMRISC Microcontroller architecture. Based on the experiment results, the embedded fault-tolerance design has produced acceptable error-recovery rate with the optimal operating frequency is peaked at 60MHz. The evaluation shows the promising results are obtained after comparison into error recovered and time latency. Overall, the integration of the fault-tolerance module in the microcontroller architecture offers a good starting point to create a reliable plat form in the embedded system design.