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Performance analysis on various low power CMOS digital design techniques

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Title: Performance analysis on various low power CMOS digital design techniques

Authors: R. C. Ismail, S. A. Z. Murad, M. N. M. Isa

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2016

Volume: 11

Issue: 6

Language: English

Keywords: full adderlow powerCMOSdigital design

Categories
Electrical Engineering (5972) Computer Engineering (1270) VLSI Design (122) Digital Circuits (26) Microelectronics (45)

Abstract

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. In this paper, three low power CMOS digital design techniques have been compared in terms of their speed, power consumption and area. For comparison purposes, 1-bit full adder circuits are constructed based on each of the design technique in 0.35 µm CMOS technology using Mentor Graphics tools.

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