DefinePK

Abstract

As the MOSFET’s size is expected to be shrunk every year, it is difficult to mitigate the short channel effect (SCE) issues arising in the device. The conventional MOSFET’s structure is no longer practical to apprehend these types of issues, especially for a device with a very small gate length (Lg). The SCE issues happen due to the reduction of the gate length (Lg), which causes the distance between the source and the drain region to become too close to each other. As a consequence, it causes the charge sharing effects between source and drain region that eventually leads to higher subthreshold swing (SS). A steep SS value around 55 to 65 mV/dec is desired in MOSFET device for faster switching operation. Therefore, a new architecture of Vertical Double Gate (DG) MOSFET device is proposed to circumvent these issues. Besides that, the process parameter variations in the device are also considered as one of the important factors that significantly affect the SS value. In this paper, an attempt to analyze the variability of multiple process parameters towards the SS value in 12nm gate length (Lg) vertical DG-MOSFET device has been made. At the end of the experiments, it was found that the most dominant process parameter that contributed a large effect on SS value was halo implantation tilt angle. The lowest possible value of SS was observed to be 62.52 mV/dec with signal-to-noise ratio (SNR) of -35.83 dB.