DefinePK

Abstract

For the full custom ASIC design, it is mandatory that every part of the system consideration has to be fulfilled with all the design specifications. In this delay in the complex circuits is an important aspect that has to be considered. In this paper, a comparative study and analysis of constant delay (CD) logic and the static logic is performed for various adders. This logic can also be applied for the CORDIC algorithm circuit that minimizes the delay in the circuit. The CD logic works with the pre-evaluated outputs that are much before the inputs that are fed to the respective stage. This gives an advantage over different styles of design when it comes for the multistage blocks. This control over the delay in the logic helps in the reduction of static power consumption at the different levels. Thus a power controlled design is also achieved along with the reduced delay. A comparative analysis of CD and static logic is been performed for different kind of adders like half adder, full adder, 16 BIT ripple carry adder and 16 BIT Wallace tree multiplier. The analysis is carried out in 120nm technology with frequency as 500 MHz and at a temperature of 450C.