DefinePK

Abstract

Most of the multiplier circuits used adders in order to reduce the vertical critical path of the partial products. But adders will create many problems like glitches, uneven signal transition; and it will take more number of steps to reduce the partial product reduction. To solve these problems, a special kind of adders that are capable to add four/six bits per decade. These adders are called compressors. The advantage of using compressors is to provide regular structure in reduction of partial product stage. The 4:2 and 6:2 compressors as processing elements (PEs) are the fundamental basic blocks for accumulating partial products during the multiplication process. In this paper, 4:2 and 6:2 compressors are designed on reversible logic using DKGP gate, one of the reversible gates and implemented in transistor level using Single electron transistor (SET). SET is considered to be popular in the field of nanoelectronics. It offers low power consumption and high operating speed. The developed compressors are simulated using SPICE software and the obtained results are compared with single electron transistor (SET) and the conventional CMOS. It is observed that the compressors using SET has considerable low power dissipation with conventional CMOS.