DefinePK

Abstract

Advances in multimedia have expanded the boundaries of communication systems and changed the communication industry over the past a few decades in the applications such as Digital TV, DVD video, HDTV, internet video streaming, video conferencing, mobile technology, patrolling, object tracking, and medical applications. Video Compression (VC) placed a significant part in the realization of these technologies by bridging the gap between the demand for quality, performance and limitations of current storage and transmission capabilities. Motion Estimation (ME) is the power hungry block in the Video Compression System (VCS). The Sum of Absolute Difference (SAD) is the most repeated operation in the motion estimation subsystem. This paper proposed the Field Programmable Gate Array (FPGA) Implementation of 4X4 SAD architecture. The design is simulated using Xilinx Integrated Software Environment (ISE) and synthesized using Xilinx Synthesis Tool (XST) on Spartan-3 FPGA board. The proposed SAD estimates area acquired and latency.