DefinePK

Abstract

In this paper we will discuss about Low speed peripheral architecture, which involves multiple I2C, SPI, UART instances, DMA engine. Given the limited number of general purpose IO ports are SOC boundary, these protocol blocks are grouped in to a single subsystem while sharing all the resources like DMA, channels and GPIO’s while interfacing with external chips. The design has been done using verilog we will be analyzing the performance of the subsystem by using System verilog & Universal verification method based test bench environment to generate various use case scenarios involving different number of I2C, SPI and UART instances. And this project is simulated using Questasim 10.2c.