DefinePK

DefinePK hosts the largest index of Pakistani journals, research articles, news headlines, and videos. It also offers chapter-level book search.

Three-coding test compression technique for SoC based design


Article Information

Title: Three-coding test compression technique for SoC based design

Authors: Chakrapani K., Saravanan, S. Muthaiah R.

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2017

Volume: 12

Issue: 21

Language: English

Categories

Abstract

Testing a system-on-chip (SoC) result in serious challenges due to the growth of volume and test power consumption of test data sets. Several compression techniques for test data came into light for reducing volume of the test data and its scan power. This paper mainly concentrates on increasing the compression ratio and power consumption for scan vectors through new three coding compression technique. This encoding scheme includes block merging along with three types of coding techniques to obtain efficient compression of scan test sets. This paper review the impact of compressed test data on consumption of power and test application time are also considerable. The actual test data is decoded with Simple decoder architecture. Experimental Results on ISCAS89 benchmark circuit shows the effective ratio of proposed method compared with prior works.


Paper summary is not available for this article yet.

Loading PDF...

Loading Statistics...