DefinePK

Abstract

Image algorithm throughput, costs, and time quality are the criteria and key factors to failure or success for every image enhancement system. In this paper, the spatial parallelism mechanism using the Field Programmable Gate Array (FPGA) platform is applying to build embedded real time system to achieve this goal. The spatial parallelism can provide the ability to speed up image processing. It includes design and implementation a system that select many algorithms to enhance image features. An FPGA development Board DE2-115 is used as vehicle system. Configuring Phase-Locked Loop (PLL) is used to increase the operating frequency to 1GHz to avoid the master clock limitation of the development Board DE2-115 board. The results of implemented design show that the throughput is increased in term of coarse-grain scale. Furthermore, an acceptable image enhancement is obtained by applying tuning process on using these algorithms.