DefinePK

Abstract

A 3.4 GHz Phase Locked Loop (PLL) with a Differential Ring oscillator is simulated in a 0.18µm CMOS process with 1.8V power supply. The reference clock frequency is 212.5 MHz with a mod 16 frequency divider the PLL generates a 3.4 GHz frequency. The proposed PLL can be locked from 2.539 GHz to 5.0793 GHz with a lock range of 2.54 GHz with 48.4% of duty cycle. The peak-peak jitter is 8.786ps with an RMS jitter of 1.18 ps and pull-in time 170ns (fast lock-in time). The PLL consumes 18.8mW power from a 1.8V power supply. PLL Blocks are simulated with 1.8V, 0.18µm CMOS Technology using Cadence-Virtuoso tool.