DefinePK

Abstract

This paper introduces the function of test cases with minimal power for Built-In-Self-Test (BIST) implementation. This method intends Test-Per-Scan (TPS) based test cases using Multiple Single Input Change (MSIC) architecture. Multiple SIC patterns are developed by using EX-OR operation of twisted ring counter and test design algorithms like Linear Feedback Shift Register (LFSR),Bit-Swapping LFSR (BSLFSR), and Cellular Automata (CA). These patterns are used to a diminish number of transitions in the test patterns that are generated. The preferred method uses Test-Per-Scan technique for generating Multiple SIC test patterns. TPS diminished the power consumption during test mode. The seed generator used in TPS is modified LFSR’s i.e., BS-LFSR, Cellular Automata (CA). BS-LFSR is composed of with an LFSR with a multiplexer. In CA, it also presents a variation on a BIST technique, which is from a one-dimensional cellular automaton; the pseudo random bit generator is generated. The proposed Hybrid Cellular Automata (HCA) using the rules 90 and 150 to generate the pseudo random designs. Moreover, the CA implementations illustrates properties of data compression like LFSRs and that they exhibit locally and with topological consistency significant attributes for a VLSI design. In this proposed method, LFSR is replaced with BS-LFSR, and HCA. Simulation and synthesis outcome with ISCAS c432 benchmark determine that Multiple SIC can reduce the power consumption.