DefinePK

Abstract

FinFET design was introduced as an alternative for CMOS due to its mitigate short channel effects at lower technology nodes and also scaling of the single bulk MOSFETs faces problems in nanometre technology due to its short scaling effect that causes leakage current to increase. Dual gate FinFET has better short channel effect because of its alignment of the gates. The previous average 8T SRAM has more area and it requires write back scheme. The full scheme local bitline (BL) swing connected to read buffer gate can be obtained with boosted word line (WL) voltage. But we cannot use this voltage because it reduces the SRAM stability and threshold voltage is high. In this paper the SRAM architecture based on FinFET using SVL circuit technique is designed. In the proposed architecture scheme of full swing is determined by cross coupled PMOSs and the gate of the read buffer is driven by full Vdd without the use of boosted wordline voltage. The SRAM based on FinFET is designed on tanner tool. By applying SVL circuit technique the leakage power and the area consumption of SRAM based on FinFET is 83.74µw and 47% which is lower than the normal FinFET based SRAM architecture.