DefinePK

Abstract

Network on Chip (NoC) router is mainly used in system on chip (SoC) application. Millions of transistor integrated into a single chip is called as very large scale integration (VLSI) to design a single integrated circuit (IC). Also, millions of IC is integrated into single chip is called as SoC. Hence, the routing is very difficult in SoC. To avoid this kind of problem, the NoC router is incorporated into SoC board. NoC router is mainly used to transmit data from source to destination based on request. To set the priority, Priority arbiter is used for which data will come first from multiple request at the time. Lot of priority arbiter is available such as regular round robin arbiter, distributive round robin arbiter, matrix arbiter… etc. FIFO or buffer is used for temporary storage. Finite state machine (FSM) act as controller of NoC router to control entire module. Network interconnect is used for linking. Multiplexing and de-multiplexing operation is carried out by Crossbar switch. The existing NoC router is designed with two programmable elements (2-PE) & single error correction with double error detection method by using hamming code. But the probability of error detection is low and speed is very less. To overcome this problem, the proposed NoC router is designed with three programmable elements (3-PE) and triple error detection is performed with less number of parity bit by using improved hamming code. Comparison between the existing and proposed router is carried out to analyze the various parameters. From the obtained results, it is illustrated that the proposed NoC router offers high speed, Low area and the highest probability of error detection than the existing NoC router. ModelSim and Xilinx ISE tools are used for simulation and synthesis process. Verilog HDL is used to design a different type of NoC router.