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Conception and hardware minimization of a new chien search block for Reed Solomon Codes with implementation on FPGA card

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Title: Conception and hardware minimization of a new chien search block for Reed Solomon Codes with implementation on FPGA card

Authors: Mohamed Elghayyaty, Azeddine Wahbi, Anas El Habti El Idrissi, Omar Mouhib, Laamari Hlou, Abdelkader Hadjoudja

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2020

Volume: 15

Issue: 11

Language: English

Categories
Electrical Engineering (5972) Hardware Implementation (4) Reed-Solomon Codes (1) Computer Engineering (1270) FPGA (50)

Abstract

Error Correcting Codes such as Reed Solomon (RS) and Bose, Chaudhuri, and Hocquenghem (BCH) are widely used in communication and storage systems in order to correct and control errors introduced by transmission channel. In this paper, a simplified algorithm for RS and BCH decoding is proposed with a view to reduce the number of components compared to the basic chien search block. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of chien search block on FPGA card.

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