DefinePK

Abstract

The repercussions of a 16 nm double-gate FinFET (DG-FinFET) design against two different optimization methods are investigated and examined. The drive current (ION) and leakage current (IOFF) ramifications towards the adjustment of six process parameter that incorporates polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose and VTH doping tilt for both L25 Orthogonal Array (OA) Grey Relational Analysis (GRA) as well as an L25 OA of Taguchi Statistical Method (TSM). However, with TSM, a consideration of noise factor in gate oxidation temperature and polysilicon oxidation temperature is included. The utilization of ATLAS and ATHENA modules enables respective design simulation as well as characterizations of device’s electrical attributes to be performed. Subsequent to the initial responses from the design simulation, implementation of both TSM and GRA have been implemented separately to assist in process parameter optimization in view to optimize the output responses. The factor percentage of Signal-to-noise ratio determined the process parameter’s effectivity. The most prominent factor is similar for both TSM and TSM-based GRA for which is the polysilicon doping tilt, whereby for L25 OA TSM, the I_ON and I_OFF obtained after the optimization are 1559.97 µA/µm and 33.03 pA/µm that brings the I_ON/I_OFF ratio to 47.23 ? 10⁶ as opposed to more insignificant 32.49 ? 10⁶ on pre-optimized simulation. Meanwhile small increment of ratio at 48.01 x 106 from respective values of 1656.27 µA/µm and 34.49 pA/µm for the TSM-based GRA proves that both optimization techniques have met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013.