DefinePK

Abstract

In this paper, an attempt to implement an optimal complex multiplier using the “Urdhva Tiryakbhyam” Sutra of the ancient Indian Vedic Mathematics is presented. Signal Processing is based on mathematical analysis of complex numbers. Many DSP operations are based on complex operations like Fast Fourier Transform, z-transform, linear systems, multimedia applications, and telecommunications. The multiplier determines system performance as it is the slowest element and generally occupies a large area. Due to such conflicting constraints designing a complex multiplier has always been a challenge with significant tradeoffs. The proposed 16-bit Complex Multiplier using Vedic Multiplication is coded in VHDL, simulated and synthesized in Xilinx Vivado 2016 Software and compared to a standard Booth Complex multiplier.