DefinePK

Abstract

The article is devoted to solving issues related to the problem of the bottlenecks" in multiprocessor computing systems, namely, conflicts for access of processors to the shared system bus. It is described the possibility of placing between the processor and the memory of the hardware-implemented module of the buffer device, which is necessary for quick access to memory (in the structure of the buffer module uses associative memory) of a multiprocessor computer system with a widely used "common bus" interface. The buffer is implemented in register memory and consists of two parts, one of which is responsible for writing data, the other for reading data. In the course of the operation, the functional organization of the hardware buffer unit was defined, the algorithms for its operation were developed and implemented, a VHDL file describing the operation of the device was created and debugged, simulation of the correctness of work in the ISE Web Pack program. Using modern element base, namely, field-programmable gate array (FPGAs), the described buffer device is reconfigurable (you can adjust the VHDL file to change the parameters of the work, and the structure and functionality at any time) and cross-platform, because of universality of VHDL-code the device can be implemented on FPGAs of different manufacturers. Thanks to the application of the described block, it is partially possible to solve the problem of the "bottleneck" of the multiprocessor system with the "common bus" interface. As the result of the practical use of the described device, the throughput of the subsystem "processor-memory" and, accordingly, the performance of the entire multiprocessor system as a whole, will increase.