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Network on-Chip Optical Interconnects – Issues and Challenges


Article Information

Title: Network on-Chip Optical Interconnects – Issues and Challenges

Authors: Khurram Aziz, Nasir -ud-Din Gohar

Journal: NUST Journal of Engineering Sciences

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Y 2015-03-12 2016-02-28

Publisher: National University of Sciences & Technology, Rawalpindi/Islamabad (NUST)

Country: Pakistan

Year: 2009

Volume: 2

Issue: 1

Language: en

DOI: 10.24949/njes.v2i1.54

Categories

Abstract

Copper wires, having served their purpose in communication networks for a long time, are now rapidly being replaced by photonics. Almost all current deployments employ photonics instead of copper. On-chip networks (NoC) seem to be headed the same way. Increasing gate speeds mean that interconnect delays have become significant and can no longer be ignored. In the 70 nm technology, the ratios between interconnect delays and gate delays can be very high. One of the effects of this increased interconnect delay is that one clock cycle is insufficient to propagate the signal across the entire chip, posing serious synchronization problems. Similarly, delay in copper interconnects and limited bandwidth forms a serious bottleneck between multi processor communications in Networks on-Chip, suggesting that the fate of copper on-chip will be similar to the fate of copper in communication networks. Recent studies suggest that photonics is a promising solution for on-chip interconnects. This study focuses on optical interconnects for Networks on-chip and looks at various techniques that have been proposed to address issues in optical interconnects.


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