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Abstract

In this paper, a new method to improve the transition delay, Conditional Pulse enhancement and reduction in transistor count for FlipFlop is proposed which consumes less power and area. The design featuring an explicit type pulse-triggered structure improves the problemarises due to transition delay. The clocked Pseudo NMOS style structure enhances the efficiency and reduces the load capacitance. Thedesign which successfully solves the long discharging path problem also reduces the transistor count in the discharge path. The Proposedcircuit is implemented using Predictive technology Model in CMOS 90-nm technology. The proposed design outperforms the existingmethod by reducing the power by 15% and 40% with two existing methods.