DefinePK

Abstract

Addition process plays an important role in nearly all the digital circuits and it remains an integral part of all the arithmetic operations, such as the multiplication, division and subtraction, to name a few. The carry select adder (CSLA) is one of the fastest adders preferred in the processors. This paper presents a novel SQRT CSLA using the XNOR block that operates at low power and utilizes less area. The structure is verified for operation and validation using 1) a standard full adder structure and 2) using an 18T transistor full adder. The 64-bit CSLA architecture has been used as a test bench. Three types of adder structures, namely, SQRT CSLA, SQRT CSLA with BEC-1 and SQRT CSLA with half adder (HA) blocks have been taken for comparison against the proposed SQRT CSLA with EXNOR blocks. The logic and circuit level modifications of the implementations using the standard full adder and 18T adder modules made in terms of the logical flow of addition process realize reduction in the number of transistors used. The validation of the circuit design is made using exhaustive simulations, inclusive of operations at various process corners and compared with the counterpart circuit architectures. The 32nm PTM technology models have been employed in the design simulations using Cadence® Virtuoso tool.