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SRAM based architecture for TCAM for low area and less power consumption


Article Information

Title: SRAM based architecture for TCAM for low area and less power consumption

Authors: Shaly Laurenceand, Anuros Thomas K.

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2015

Volume: 10

Issue: 17

Language: English

Categories

Abstract

Ternary content addressable memories (TCAMs) perform high-speed search and network routing operations in a deterministic time. When compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. This paper proposes an efficient memory architecture, which emulates the TCAM functionality with SRAM. This logically divides the classical TCAM table along columns and rows into hybrid TCAMsubtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced.


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