DefinePK

Abstract

In recent years, Field Programmable Gate Arrays are used as reconfigurable architecture in various platforms as a special type processor which allows the end user to configure directly. The Logic Blocks and switch matrix provides an extensive use in the reconfigurable computing, that can be configured according to required application which also consumes lots of standby power with reduced throughput. This project investigates in optimizations of reconfigurable FPGA cells that involves in two stages, optimization of Lookup Table (LUT) in Logic Blocks for Large Application and optimization of switch matrix with encoding techniques. The proposed encoding technique combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding; Lookup Table consists of 8 inputs which are extensively used for large applications; sleep controller design is used for reducing the standby power consumed by the LUT. The proposed architecture is designed, evaluated and simulated using Xilinx SPARTAN 3E (X3SC50).