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Design of modified 32 bit booth multiplier for high speed digital circuits


Article Information

Title: Design of modified 32 bit booth multiplier for high speed digital circuits

Authors: P. Nithiyanandham, V. Balamurgan

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2015

Volume: 10

Issue: 10

Language: English

Categories

Abstract

This paper presents the design and implementation of Advanced Modified Booth Encoding (AMBE) multiplier for both signed and unsigned 32 - bit numbers multiplication the array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requirement of the modern computer system is a dedicated and very high speed unique multiplier unit for signed and unsigned numbers. Therefore, this paper presents the design and implementation of AMBE multiplier that can be suitable for the high speed digital logic circuits. The Carry looks ahead Adder (CLA) tree and the final Carry Look ahead (CLA) adder used in combination of CBEL (Common Boolean Enable Logic) to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system.


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