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19 Papers found for "Arithmetic Circuits (19)"

Design and analysis of partition technique based Dadda multiplier architecture

C. Nalini, C. Padma, D. Kalaiyarasi, G. Nagarajan, M. Sundar Raj, T. Suguna

ARPN Journal of Engineering and Applied Sciences | 2025

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Performance optimized group decomposition Dadda multiplier for DSP applications

C. Padma, K. Venkata Lakshmi Keerthi, Kalaiyarasi D., Padarti Vijaya Kumar, R. Kiran Kumar, Suguna T.

ARPN Journal of Engineering and Applied Sciences | 2025

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Implementation of area efficient and high speed HNG gate based multiplier for DSP applications

K. Manikanta, N. Siddaiah

ARPN Journal of Engineering and Applied Sciences | 2022

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Implementation of area efficient and high speed HNG gate based multiplier for DSP applications

K. Manikanta, N. Siddaiah

ARPN Journal of Engineering and Applied Sciences | 2022

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Performance evaluation of reversible Vedic multiplier

Gowthami P., R. V. S. Satyanarayana

ARPN Journal of Engineering and Applied Sciences | 2018

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Intend of power-delay optimized Kogge Stone based Carry Select Adder

P. Manimegalai, Prajoona Valsalan

ARPN Journal of Engineering and Applied Sciences | 2018

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Power efficient Wallace tree multiplier using Full Swing Gate Diffusion Input technique

Anitha Juliette Albert, Mohammed Farook, Seshasayanan Ramachandran, Syed Mustafaa

ARPN Journal of Engineering and Applied Sciences | 2018

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Design of Modified Russian Peasant Multiplier using MSQRTCSLA based adder

B. Justus Rabi, C. Uthaya Kumar

ARPN Journal of Engineering and Applied Sciences | 2016

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Design and performance analysis of BCSE algorithm and Han Carlson adder based MAC unit

Oindrila Bhattacharya, T. Ravi, V. Vijayakumar

ARPN Journal of Engineering and Applied Sciences | 2016

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Prominent speed arithmetic unit architecture for proficient ALU

D. Roshini Keerthana, P. Umarani, R. Rashvenee, T. Ravi

ARPN Journal of Engineering and Applied Sciences | 2016

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