DefinePK

Abstract

This paper proposes the design and gate level implementation of a low power and area efficient 8-bit Wallace tree multiplier design using Full Swing Gate Diffusion Input Logic technique. The proposed design, developed using 45nm process technology was compared with its equivalent design, developed using conventional CMOS technology. The proposed multiplier presented significant advantages in terms of power, delay and area. Power and delay analysis of the proposed multiplier was performed for varied gate oxide thickness and three process technologies - 130 nm, 70nm and 45 nm. The design was subjected to parametric variations, such as gate oxide thickness and channel length. The results conclude to two major inferences. Firstly, in applications that demand low power, the proposed Full Swing Gate Diffusion Input Logic Wallace tree multiplier will be an ideal replacement for conventional CMOS multiplier, owing to reduced power and area. The proposed multiplier offers 26.21% reduction in power, 12 % reduction in delay and 36% reduction in area when compared to its equivalent CMOS version. Secondly, as transistor dimensions reduce, parametric variations become more significant. This analysis will aid in drastic reduction of parametric yield loss.