DefinePK

Abstract

In computation designs, the arithmetic operation plays a major role in all type of logical designs. It decides the performance of all internal components and its behavior. Hence, recent researchers focused on obtaining the high speed of operation with minimal power consumption. The conventional Carry Select Adder results in more area due to the inbuilt nature of two Ripple Carry Adders in the same structure. Similarly, the AND-OR-Invert based Carry Select Adder consists of complex circuits for processing the basic operation. Hence, a Kogge–Stone adder based carry select adder is designed, which is replacing the AOI logic from the previous AND-OR-Invert based Carry Select Adder to achieve optimization in terms of area, delay, and power. The proposed design is synthesized and simulated under cadence 45nm CMOS technology. The comparison shows how the proposed KS-CSLA is better than the existing regular dual Ripple Carry Adder (RCA), modified adder with BEC concept, Dual RCA and modified Square root adder with BEC unit. Finally, the speed of proposed model is increased twice of the speed of dual RCA.