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Performance evaluation of reversible Vedic multiplier


Article Information

Title: Performance evaluation of reversible Vedic multiplier

Authors: Gowthami P., R. V. S. Satyanarayana

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2018

Volume: 13

Issue: 3

Language: English

Categories

Abstract

Multipliers are one of the building blocks of several computational units. The speed of the computational units is determined by the speed of the multipliers. To increase the speed of computational units, faster multipliers should be utilized. The Vedic multiplier is one such solution, which is capable of performing the quicker multiplications. In Vedic mathematics Urdhva Tiryakbhayam sutra discards the non essential steps in multiplication process which in turn increases the speed of a multiplier. In this work, the performance of the Urdhva Tiryakbhayam Vedic multiplier is improved by reducing the Number of gates, Garbage outputs, Quantum cost and TRLIC.


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