DefinePK

Abstract

ALU is one of the most important unit of processor. The computing efficiency of the processor depends on the competency of the ALU. ALU unit performs the arithmetic and logical operations. The adder and multiplier are the main computational units of the arithmetic unit. The performance factors such as delay, power and area. Parallel prefix adders have better delay performance; it involves the execution of the operation in parallel. Brent Kung adder is the most area and power efficient parallel prefix adder. In this paper we proposed high speed Brent Kung adder which consists of Urdhava Tiryakbhyam sutra based Vedic multiplier. In the conventional multiplier speed is restricted by the adders used for partial products. The proposed multiplier is used in the arithmetic unit of an ALU shows better performance in terms of delay. The proposed arithmetic architecture is designed, evaluated and implemented in Xilinx FPGA.