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Implementation of area efficient and high speed HNG gate based multiplier for DSP applications


Article Information

Title: Implementation of area efficient and high speed HNG gate based multiplier for DSP applications

Authors: K. Manikanta, N. Siddaiah

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2022

Volume: 17

Issue: 13

Language: English

Categories

Abstract

In the scientific literature, there is a lot of discussion on approximate multipliers and circuits based on approximate 4-2 compressors. The designer who wants to employ an approximation 4-2 compressor is confronted with the challenge of choosing the proper topology due to the enormous number of options. A complete study and comparison of the roughly 4-2 compressors that have been suggested in the literature are presented here. One more compressor is shown, so that there are now twelve distinct approximate 4-2 compressors evaluated. The goal is to create logic gates that can be reversed. Quantum computing relies heavily on the reversibility of logical operations. This technology's gadgets run at very fast speeds and utilize very little power. Hardware description language (HDL) is used to create simple reversible logic gates. The Verilog implementation of the Wallace tree multiplier uses a simple half adder and a full adder. The reversible logic gates have been created, as well as a 4bit reversible adder, irreversible adder along multiplier has been developed. Layouts are designed using a variety of foundry technologies, and these methods are compared. We've reached the end of the road in terms of low-power dissipation. An 8x8 bit reversible multiplier circuit has been suggested and developed in this article. In terms of speed and complexity, the suggested reversible multiplier is superior to the current multipliers. In terms of the number of gates, garbage outputs, and constant inputs, it is superior to the current alternatives. The \HNG\" 8x8 reversible gate was recently suggested by Haghparast and Navi. It is possible to use a reversible HNG gate as a reversible full adder when it is used alone. The reversible multiplier circuit in this study is built using HNG gates. Two 8-bit binary integers may be multiplied using the HNG gate in the proposed reversible multiplier circuit. A generalized version of the suggested reversible 8x8 multiplier circuit may be used for NxN bit multiplication as well."""


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