DefinePK

Abstract

This paper presents the analysis of Multiply-Accumulate (MAC) architecture for DSP applications. In VLSI, arithmetic cells including adders and multipliers are the most commonly used components. A MAC unit consists of a multiplier in combinational logic followed by an adder and an accumulator register that stores the result. Efficient implementation of MAC Unit is crucial in most of the microprocessors and digital signal processors (DSPs). An efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm may be used to design an efficient MAC Unit.4-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This is capable of reducing the average switching activity of the multiplier block. The proposed architecture was applied to MAC unit and compared against the conventional compressor based MAC units and applied to DSP applications to check its performance. To speed up the addition, Han Carlson adder is introduced. Parallel prefix adders provide good results as compared to the conventional adders.