DefinePK

Abstract

Multiplication and Accumulation (MAC) unit is recognized as high potential in every Digital Signal Processors (DSP). Multiplication is one of the essential operations every DSP applications such as Fast Fourier Transform (FFT), Digital Filters and so on. In this paper, Modified Russian Peasant Multiplier (MRPM) is designed through Very Large Scale Integration (VLSI) System design environment. The Russian Peasant Multiplier (RPM) is the best multiplication technique for improving their hardware performances. It makes the Partial Product Generation (PPG) process with the help of Multiplexers. Further Carry Select Adder (CSLA) is used in RPM based multiplier for reducing the hardware. However, still it required high speed MAC computational unit for up growing Fourth Generation (4G) based Wireless communication applications. To meet this requirement, MRPM based efficient multiplier is developed in this paper. In proposed MRPM, Modified Square Root Carry Select Adder (MSQRTCSLA) is used for performing addition operation. Further Reduced Wallace Tree Reduction (RWTR) is used in proposed design for simplifying the PPG results. Proposed MSQRTCSLA based MRPM multiplier offers 20.31% reduction in delay consumption and 61.31% reduction in power consumption than best existing Bi-Recoder based MAC unit.