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Title: Design of low power high speed DRAM architecture using dual edge triggered flip flop
Authors: Manoranjitham M, Vijayashaarathi S
Journal: ARPN Journal of Engineering and Applied Sciences
Publisher: Khyber Medical College, Peshawar
Country: Pakistan
Year: 2015
Volume: 10
Issue: 8
Language: English
Memory power consumption plays a major role in the multi-core computer platforms. Now a day, the bandwidth and the capacity of the memory data rate is increased. Due to that, the power consumption becomes higher and higher in the memory which covers a maximum power consumption in the system .Generally, conventional memory system do not provide an efficient mechanism for managing its power and performance tradeoff. Mini-rank architecture is designed for the DDRx memories by breaking each DRAM rank into multiple narrow mini-ranks and activates only fewer devices for each request which reduces the memory power consumption. This technique will cover large area due to different mini-rank configurations in the memory and the data transfer in the signal is slightly slow due to single edge triggered flip-flop. Thus, the structure of the mini-rank architecture is designed efficiently by combining different configuration in the common memory by introducing memory select line for selecting the x32, x16, and x8 bit configurations and also dual edge triggered flip flop is implemented in the memory to reduce the count of the clock cycle.
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